1. Field of the Invention
The present invention relates to an apparatus and method for data transmission, and more particularly, to an apparatus and method for data transmission and an apparatus and method for driving an image display device using the same, in which the transition of data values is minimized during data transmission to minimize electromagnetic interference.
2. Discussion of the Related Art
The trend in the information display industry is towards various flat panel displays that have reduced weight and volume compared to cathode ray tubes. Examples of such flat panel displays include liquid crystal displays (LCD), field emission displays (FED), plasma display panels (PDP), and light emitting displays (LED).
Notably, the LCD displays a picture image by controlling the light transmittance of liquid crystal cells depending on video signals. An active matrix type LCD is provided with switching elements formed in each liquid crystal cell and is suitable for displaying moving pictures. Thin film transistors (TFTs) are mainly used as the switching elements used for the active matrix type LCD.
FIG. 1 illustrates a related art apparatus for driving an LCD.
Referring to FIG. 1, the related art apparatus for driving an LCD includes an image display unit 2 including liquid crystal cells formed in each region defined by first to nth gate lines GL1 to GLn and first to mth data lines DL1 to DLm, a data driver 4 supplying analog video signals to the data lines DL1 to DLm, a gate driver 6 supplying scan pulses to the gate lines GL1 to GLn, and a timing controller 8 aligning source RGB data from external input to supply them to the data driver 4, generating data control signals DCS to control the data driver 4, and generating gate control signals GCS to control the gate driver 6.
The image display unit 2 includes a transistor array substrate, a color filter array substrate, a spacer, and a liquid crystal. The transistor array substrate and the color filter array substrate face each other and are bonded to each other. The spacer uniformly maintains a cell gap between the two substrates. The liquid crystal is filled in a liquid crystal area prepared by the spacer.
The image display unit 2 includes a TFT formed in the region defined by the gate lines GL1 to GLn and the data lines DL1 to DLm, and the liquid crystal cells connected to the TFT. The TFT supplies analog video signals from the data lines DL1 to DLm to the liquid crystal cells in response to the scan pulses from the gate lines GL1 to GLn. The liquid crystal cell is comprised of common electrodes facing each other with liquid crystal therebetween and pixel electrodes connected to the TFT. Therefore, the liquid crystal cell is equivalent to a liquid crystal capacitor Clc. The liquid crystal cell includes a storage capacitor Cst that retains the analog video signals filled in the liquid crystal capacitor Clc until the next analog video signals are filled therein.
The timing controller 8 aligns the externally input RGB source data to make it suitable for driving the image display unit 2 and supplies the aligned data to the data driver 4. Also, the timing controller 8 generates the data control signals DCS and the gate control signals GCS using a main clock MCLK, a data enable signal DE, and horizontal and vertical synchronizing signals Hsync and Vsync, which are externally input, so as to control each driving timing of the data driver 4 and the gate driver 6.
The gate driver 6 includes a shift register that sequentially generates scan pulses, i.e., gate high pulses in response to a gate start pulse (GSP) and a gate shift clock (GSC) among the gate control signals GCS from the timing controller. The gate driver 6 sequentially supplies the gate high pulses to the gate lines GL of the image display unit 2 to turn on the TFT connected to the gate lines GL.
The data driver 4 converts the data RGB aligned from the timing controller 8 into the analog video signals in response to the data control signals DCS supplied from the timing controller 8 and supplies to the data lines DL1 to DLm the analog video signals corresponding to one horizontal line per one horizontal period in which the scan pulses are supplied into the gate lines GL1 to GLn. In other words, the data driver 4 selects a gamma voltage having a predetermined level depending on a gray level value of the data RGB and supplies the selected gamma voltage to the data lines DL1 to DLm. At this time, the data driver 4 inverses polarity of the analog video signals supplied to the data lines DL in response to a polarity control signal (POL).
FIG. 2 illustrates a data transmission bus between the timing controller and the data driver shown in FIG. 1.
Referring to FIG. 2 in connection with FIG. 1, the timing controller 8 includes a control signal generator 22 generating the control signals DCS and GCS, and a data aligner 24 aligning the source data RGB and supplying the aligned data to the data driver 4.
The control signal generator 22 generates the gate control signals GCS (GSC, GSP and GOE) and the data control signals DCS (SSC, SSP, SOE and POL) using the main clock MCLK, the data enable signal DE, and the horizontal and vertical synchronizing signals Hsync and Vsync, which are externally input.
The gate control signals GCS are supplied to the gate driver 6 through respective transmission lines included in a gate control signal bus (not shown). The data control signals DCS are supplied to the data driver 4 through respective transmission lines included in a data control signal bus 12.
The data aligner 24 aligns the externally input RGB source data to be suitable for a bus transmission manner and synchronizes the aligned RGB data with a source shift clock (SSC) signal to supply the synchronized data to the data driver 4. For example, the data aligner 24 supplies the aligned RGB data to the data driver 4 through red, green and blue data buses 14, 16, and 18 as shown in Table 1. If the RGB source data are 6-data bit, each of the data buses 14, 16 and 18 is comprised of six data transmission lines. As a result, the number of the data transmission lines becomes 18.
TABLE 1Bit Grey levelD5D4D3D2D1D00000000100000120000103000011.....................63 111111
In Table 1, D0˜D5 represent one of R, G, and B data values.
The timing controller 8 supplies data corresponding to one pixel (for example, 18 bits of respective 6 bits of R, G, and B) to the data driver 4 using eight data transmission lines 14, 16, and 18. However, if the data corresponding to one pixel are supplied from the timing controller 8 to the data driver 4, electromagnetic interference seriously occurs due to transition of the data.
For example, if the current pixel data has a bit value of “0” and the next pixel data has a bit value of “1”, transition occurs in all the bits causing high electromagnetic interference. Particularly, if resolution and size of the image display unit increase, the problem electromagnetic interference becomes more serious.